1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming isolation structures and fins on a FinFET semiconductor device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width under the channel and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
Both FET and FinFET semiconductor devices have an isolation structure, e.g., a shallow trench isolation structure, that is formed in the semiconducting substrate around the device so as to electrically isolate the semiconductor device. FIGS. 1A-1D depict various illustrative problems that may be encountered in forming isolation structures on FinFET semiconductor devices. In general, as shown in FIG. 1A, formation of the fins 16 for a FinFET device 10 involves etching a plurality of trenches 14 in a semiconducting substrate 12 that essentially define the fins 16. The etching process is generally performed through a patterned hard mask layer 18 that may be comprised of a layer of silicon nitride 18A and a layer of silicon dioxide 18B.
As FinFET devices 10 have been scaled to meet ever increasing performance and size requirements, the width 16W of the fins 16 has become very small, e.g., 6-12 nm, and the fin pitch 16P has also been significantly decreased, e.g., the fin pitch 16P may be on the order of about 30-60 nm. Traditionally, isolation structures were always the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the semiconductor device. In the case of a FinFET device, this involved masking the previously formed isolation structure and etching the trenches in the substrate that defined the fins.
However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form a so-called “sea-of-fins” across the substrate, and thereafter remove some of the fins where larger isolation structures will be formed. FIG. 1A depicts an illustrative FinFET device 10 that is at the point of fabrication where the “sea-of-fins” has been initially formed in the substrate 12. Using this “sea-of-fins” type manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 16 to very small dimensions due to the more uniform environment in which the etching process that forms the trenches 14 is performed. In the example depicted in FIGS. 1A-1B, the fins 16 all have a single uniform spacing. However, in a real-world device, the fins 16 may be formed so as to have various regions with different spacing or fin pitches 16P.
After the “sea-of-fins” has been formed, some of the fins 16 must be removed to create room for or define the spaces where isolation regions will ultimately be formed. FIG. 1B depicts the device 10 after several process operations have been formed. Initially, an optical planarization layer (OPL) 23 is formed so as to overfill the trenches 14. Thereafter, an anti-reflective coating layer (ARC) 24 is formed above the OPL layer 23 and a patterned mask layer 26, e.g., a patterned photoresist mask, is formed above the ARC layer 24. The mask layer 26 has a plurality of openings 26A-26C positioned above various fins 16 to be removed. In the depicted example, only a single fin will be removed to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin 16 may be removed. The ARC layer 24 may be comprised of a variety of materials, such as, for example, silicon nitride, silicon oxynitride, silicon or carbon containing organic polymers, etc.
In some cases, with very tight fin pitches, the lithography and etching processes that are performed to define the trenches 14 in the substrate 12 may introduce variables that can lead to damaged fins 16. For example, in FIG. 1B, the openings 26B-26C have a dimension 28 that is precisely as intended by the design process, whereas the opening 26A has a dimension 30 that is greater than that of dimension 28. The variations in the dimensions 28, 30 may be due to acceptable process variations in the lithography operations that are performed to make the patterned mask layer 26. Overlay errors in attempts to properly locate the openings 26A-26C may also lead to problems that may cause fin damage when the trenches 14 are formed.
The trench etching process that is performed to form the trenches 14 should be non-selective in nature, i.e., the etchants used may consume the litho film material (such as the OPL layer 23) and the fins 16. The trench etching process may also introduce undesirable process variations in the size of the openings that are formed through the ARC layer 24 and the OPL layer 23 to remove the fins 16 under the openings 26A-26C. In FIG. 1B, the dashed line 32 depicts the idealized pattern of the opening that will be formed in removing the selected fins 16. The dashed line 34 depicts the situation where, due to variations in the etching process, the openings are wider than desired. In the case where the openings that will be formed to remove a selected number of fins 16 is too large, the fins 16 that will become part of the final FinFET device 10 may become damaged. For example, in the dashed line region 36, an undesirably wide opening in the OPL layer 23 and the ARC layer 24, as reflected by the dashed line 34, may actually consume some of the fin 16.
FIGS. 1C-1D depict an illustrative example wherein a FinFET device 10 will be formed above an SOI (silicon-on-insulator) structure 40. In general, the SOI structure 40 is comprised of a bulk semiconducting substrate 40A, a buried insulation layer 40B (“BOX” layer) and an active layer 40C comprised of a semiconducting material. In general, the fins 16 will be formed in the active region 40C above the buried insulation layer 40B. FIG. 1C depicts the device 10 at the point where the “sea-of-fins” 16 have been formed, and the OPL layer 23, the ARC layer 24 and the patterned mask layer 26 have been formed above the fins 16. Also depicted in FIG. 1C are dashed lines 32 that depict the idealized location of the openings that will be formed in removing the selected fins 16. One problem encountered when removing some of the fins 16 positioned above the buried insulation layer 40B, is that the non-selective, fin-removal etching process that is performed to remove the ARC layer 24, the OPL layer 23 and the fin 16 may consume some of the buried insulation layer 40B in the regions enclosed by dashed lines 35. FIG. 1D depicts the device 10 after the non-selective, fin-removal process has been performed to define the openings 36 and thereby remove the selected fins 16. Eventually, isolation regions (not shown) will be formed in the openings 36. As can be seen in FIG. 1D, the non-selective, fin-removal etching process undesirably consumed some of the buried insulation layer 40B. This gouging of the buried insulation layer 40B can lead to undesirable gate-to-gate shorts when the gates are filled with a metal material.
In the examples shown in FIGS. 1A-1D, the methods involved formation of the OPL layer 23 and the ARC layer 24. However, there are other materials that may be more desirable to use during the fin removal process due to differences in etch selectivity. For example, the OPL layer 23 may be replaced with a layer of amorphous or spin-on carbon, which typically does not require the use of an ARC layer. However, when an amorphous carbon or spin-on glass material is used, a protection layer of, for example, silicon oxynitride is typically formed above the amorphous carbon or spin-on carbon material to provide a means to re-work the wafer in situations where there was an error in forming the patterned mask layer 26. In another material combination, the OPL layer 23 and the ARC layer 24 may be replaced with a DUO material that has anti-reflective coating type properties due to the manner in which it manufactured. Yet another material combination that has been employed involves replacing the OPL layer 23 with a spin-on-glass (SOG) material. The ARC layer 24 would also be employed with the SOG material.
The present disclosure is directed to various methods of forming isolation structures and fins on a FinFET semiconductor device that may solve or reduce one or more of the problems identified above.